/*****************************************************************************
*    Copyright (C)2003 Ali Corporation. All Rights Reserved.
*
*    File:    nim_mt312.h
*
*    Description:    Header file in LLD.
*    History:
*           Date            Athor        Version          Reason
*	    ============	=============	=========	=================
*	1.	Jun.12.2003     George jiang     Ver 0.1    Create file.
*	2.  Aug.27.2003		Justin Wu	     Ver 0.2    Clean up
*****************************************************************************/

#ifndef __LLD_NIM_MT312_H__
#define __LLD_NIM_MT312_H__

#include <sys_config.h>
#include <types.h>
#include <retcode.h>
#include <hld/nim/nim_dev.h>


#define NIM_MT312_ID_MT312		0x03
#define NIM_MT312_ID_MT10312	0x04
#define NIM_MT312_ID_MT10313	0x05

#define NIM_MT312_HW_IQ_INV		0		/* IQ inverted in board */
#define NIM_MT312_TM_IQ_INV		0		/* IQ inverted in transmiter */

/* Frequence search range, or step for search */
#define NIM_MT312_FREQ_SEARCH_RANG	8
#define NIM_MT312_FREQ_SEARCH_RANGA	1

/* Loop limit for autoscan */
#define NIM_MT312_TUN_LOCK_TIME	10
#define NIM_MT312_FEC_LOCK_TIME	2000

/* For wait QPSK lock status */
#define NIM_MT312_BAUD_SRCH_DONE	0x20
#define NIM_MT312_FREQ_SRCH_DONE	0x40
#define NIM_MT312_QPSK_SWEEP_ON		0xc0

/* Bit Masking defines for lock status */
#define NIM_TUNER_LOCK_TEST     0x40	/* Tuner lock */
#define NIM_QPSK_LOCK_TEST      0x02	/* C & T lock */
#define NIM_FEC_LOCK_TEST       0x0C	/* Descrambler + Byte Align in FEC status */

/* bits in diseqc mode register and prevDiseqcReg*/
#define DISEQC_REG_HORIZ		0x40	/* horizontal polarisation bit*/
#define DISEQC_REG_TONEBITS	    0x07	/* mask out the tone control bits only*/

/* Useful defaults constant*/
#define NIM_MON_SYMRATE			0x03	/* select monitor register for symbol rate read*/
#define IAI						0x80

#define UINT32_MAX				0xFFFFFFFF
#define VIT_BER_PER				20

/*
MPEG settings in SControlSnim.MPEG
the following map to Register 0x60
*/
#define NIM_MT312_MOCLK_MAN		0x80	/* MOCLK_MANUAL: See manual. Used with DIS_SR. */
#define NIM_MT312_BKERR_INV		0x40	/* invert the \BKERR output pin*/
#define NIM_MT312_MOCLK_INV		0x20	/* set (default) to invert the MPEG output clock*/
#define NIM_MT312_EN_TPS_EN		0x10	/* set (default) to enable SNIM_TPS error indicator in mpeg packet header*/
#define NIM_MT312_MPEG_SERIAL	0x08	/* serial mode on MDO0 pin*/
#define NIM_MT312_OPCTRL_MASK	0xF8	/* all the above bits */

/* Register map  Address,Bytecount*/
#define NIM_MT312_IRQ_REGS      0		/* QPSK and FEC*/
#define NIM_MT312_QPSK_INT_L	2		/* QPSK interrupt status */
#define NIM_MT312_FEC_INT		3		/* contains DiseqC interrupt*/
#define NIM_MT312_QPSK_LOCK     2		/* Used for QPSK lock testing*/
#define NIM_MT312_STATUS        4		/* QPSK and FEC*/
#define NIM_MT312_FEC_STATUS    6
#define NIM_MT312_LNB_FREQ      7
#define NIM_MT312_M_SNR         9
#define NIM_MT312_VIT_ERRCNT    11
#define NIM_MT312_RS_BERCNT     14
#define NIM_MT312_RS_UBC        17
#define NIM_MT312_SIG_LEVEL     19
#define NIM_MT312_GPP_CTRL      20
#define NIM_MT312_RESET         21
#define NIM_MT312_DISEQC_MODE   22
#define NIM_MT312_SYM_RATE_H	23
#define NIM_MT312_SYM_RATE      23
#define NIM_MT312_VIT_MODE      25
#define NIM_MT312_QPSK_CTRL     26
#define NIM_MT312_GO            27
#define NIM_MT312_IRQ_ENABLE    28		/* QPSK and FEC*/
#define NIM_MT313_IE_FEC        31
#define NIM_MT312_QPSK_STAT_EN  32
#define NIM_MT312_FEC_STAT_EN   33
#define NIM_MT312_SYS_CLK       34
#define NIM_MT312_DISEQC_RATIO  35
#define NIM_MT312_DISEQC_INSTR  36		/* reg 36 with auto increment supression*/
#define NIM_MT312_FR_LIM        37
#define NIM_MT312_FR_OFF        38
#define NIM_MT312_AGC_CTRL      39
#define NIM_MT312_FE_AGC_INIT   40
#define NIM_MT312_FE_AGC_REF    41
#define NIM_MT312_FE_AGC_MAX    42
#define NIM_MT312_FE_AGC_MIN    43
#define NIM_MT312_FE_AGC_LK_TH  44
#define NIM_MT312_TS_AGC_LK_TH  45
#define NIM_MT312_AGC_PWR_SET   46
#define NIM_MT312_QPSK_MISC     47
#define NIM_MT312_SNR_THS_LOW   48
#define NIM_MT312_SNR_THS_HIGH  49
#define NIM_MT312_TS_SW_RATE    50
#define NIM_MT312_TS_SW_LIM_L   51
#define NIM_MT312_TS_SW_LIM_H   52
#define NIM_MT312_CS_SW_RATE_1  53
#define NIM_MT312_CS_SW_RATE_2  54
#define NIM_MT312_CS_SW_RATE_3  55
#define NIM_MT312_CS_SW_RATE_4  56
#define NIM_MT312_CS_SW_LIM     57
#define NIM_MT312_TS_LPK        58
#define NIM_MT312_CS_KPROP      61
#define NIM_MT312_CS_KINT       63
#define NIM_MT312_QPSK_SCALE    65
#define NIM_MT312_TLD_OUTLK_TH  66
#define NIM_MT312_TLD_INLK_TH   67
#define NIM_MT312_FLD_TH        68
#define NIM_MT312_PLD_OUTLK3    69
#define NIM_MT312_PLD_OUTLK2    70
#define NIM_MT312_PLD_OUTLK1    71
#define NIM_MT312_PLD_OUTLK0    72
#define NIM_MT312_PLD_INLK3     73
#define NIM_MT312_PLD_INLK2     74
#define NIM_MT312_PLD_INLK1     75
#define NIM_MT312_PLD_INLK0     76
#define NIM_MT312_PLD_ACC_TIME  77
#define NIM_MT312_SWEEP_PAR     78
#define NIM_MT312_STARTUP_TIME  79
#define NIM_MT312_LOSSLOCK_TH   80
#define NIM_MT312_FEC_LOCK_TM   81
#define NIM_MT312_LOSSLOCK_TM   82
#define NIM_MT312_VIT_ERRPER	83
#define NIM_MT312_HW_CTRL		84
#define NIM_MT312_VIT_SETUP     86
#define NIM_MT312_VIT_REF3      90
#define NIM_MT312_VIT_MAXERR    94
#define NIM_MT312_BA_SETUP      95
#define NIM_MT312_OP_CTRL       96
#define NIM_MT312_FEC_SETUP     97
#define NIM_MT312_PROG_SYNC     98
#define NIM_MT312_AFC_SEAR_TH   99
#define NIM_MT312_CSACC_DIF_TH  100
#define NIM_MT312_QPSK_LK_CT    101
#define NIM_MT312_QPSK_ST_CT    102
#define NIM_MT312_MON_CTRL      103
#define NIM_MT312_QPSK_RESET    104
#define NIM_MT312_QPSK_TST_CT   105
#define NIM_MT312_QPSK_TST_ST   106
#define NIM_MT312_TEST_R        107
#define NIM_MT312_AGC           108
#define NIM_MT312_FREQ_ERR      111		/* block of 5 registers */
#define NIM_MT312_TS_ACC        116
#define NIM_MT312_DISEQC2_INT   118
#define NIM_MT312_DISEQC2_STAT  119
#define NIM_MT312_DISEQC2_FIFO  120
#define NIM_MT312_DISEQC2_CTRL1 121
#define NIM_MT312_DISEQC2_CTRL2 122
#define NIM_MT312_MONITOR       123
#define NIM_MT312_TEST_MODE     125
#define NIM_MT312_ID            126
#define NIM_MT312_CONFIG        127

#endif	/* __LLD_NIM_MT312_H__ */
